The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to the field of electrostatic discharge (ESD) protection in high speed, high precision analog and mixed-signal applications, especially for fail-safe circuits.
Integrated circuits (ICs) may be severely damaged by electrostatic discharge (ESD) events. A major source of ESD exposure to ICs is from the charged human body (described by the xe2x80x9cHuman Body Modelxe2x80x9d, HBM); the discharge of the human body generates peak currents of several amperes to the IC for about 100 ns. A second source of ESD is from metallic objects (described by the Machine modelxe2x80x9d, MM); it can generate transients with significantly higher current levels than the HBM ESD source. A third source is described by the xe2x80x9ccharged device modelxe2x80x9d (CDM), in which the IC itself becomes charged and discharges to ground in the opposite direction than the HBM and MM ESD sources (and in less than 500 ps). More detail on ESD phenomena and approaches for protection in ICs can be found in A. Amerasekera and C. Duvvury, xe2x80x9cESD in Silicon Integrated Circuitsxe2x80x9d (2nd edition, John Wiley and Sons LTD. London, 2002), and C. Duvvury, xe2x80x9cESD: Design for IC Chip Quality and Reliabilityxe2x80x9d (Int. Symp. Quality in El. Designs, 2000, pp. 251-259; ref. of recent literature).
ESD phenomena in ICs are growing in importance as the demand for higher operating speed, smaller operating voltages, higher packing density and reduced cost drives a reduction of all device dimensions. This generally implies thinner dielectric layers, higher doping levels with more abrupt doping transitions, and higher electric fieldsxe2x80x94all factors that contribute to an increased sensitivity to damaging ESD events.
The most common protection schemes used in metal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolar transistor associated with an nMOS device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be set by varying the nMOS device width from the drain to the source under the gate oxide of the nMOS device. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor operating in the snapback region under pin positive with respect to ground stress events.
The dominant failure mechanism, found in the nMOS protection device operating as a parasitic bipolar transistor in snapback conditions, is the onset of second breakdown. Second breakdown is a phenomenon that induces thermal runaway in the device wherever the reduction of the impact ionization current is offset by the thermal generation of carriers. Second breakdown is initiated in a device under stress as a result of self-heating. The peak nMOS device temperature, at which second breakdown is initiated, is known to increase with the stress current level.
Many circuits have been proposed and implemented for protecting ICs from ESD. One method is biasing the substrate of ESD protection circuits in an IC. Such substrate biasing can be effective in improving the response of a multi-finger MOS transistor which is used to conduct an ESD discharge to ground.
In the recent U.S. Pat. No. 5,940,258, issued Aug. 17, 1999 (Duvvury, xe2x80x9cSemiconductor ESD Protection Circuitxe2x80x9d), a substrate pump ESD protection bias technique has been described for standard epitaxial and non-epitaxial devices. This concept has been successfully applied to bulk CMOS technologies, including devices with thin epitaxial silicided features. The drive circuit in this technique, however, may have a relatively high and non-linear capacitance, and significant leakage current.
Economic needs drive the integration of analog, digital and RF circuits on the same chip with the same substrate. Substrate noise generated by digital circuitry couples to the RF/analog inputs through large, non-linear ESD parasitic capacitance and thus degrades the performance of analog circuitry. Furthermore, xe2x80x9chot insertionxe2x80x9d requirement in today""s electronic devices demands a fail-safe (i.e., no diode to Vdd) ESD design. How to achieve an ESD protection circuit with small and linear parasitic capacitance while maintaining a fail-safe feature, becomes a challenge for the ESD designer.
An urgent need has therefore arisen for a coherent, low-cost method of compact ESD protection devices compatible with fail-safe operation, linear analog circuits, especially high speed, high precision analog or mixed signal applications, and offering good noise immunity. The device structures should further provide excellent electrical performance, mechanical stability and high reliability. The fabrication method should be simple, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations, especially in CMOS technology. Preferably, these innovations should be accomplished without extending production cycle time, and using the installed equipment, so that no investment in new manufacturing machines is needed.
The invention discloses an integrated circuit protecting an I/O pad against an ESD pulse, wherein said circuit has in the same substrate a discharge sub-circuit and a drive sub-circuit; each sub-circuit includes an MOS transistor and comprises a direct connection between the I/O pad and the drain of the drive sub-circuit MOS transistor. The circuit further has a forward diode inserted between the I/O pad and the drain of the discharge sub-circuit MOS transistor to isolate the junction capacitance of the discharge sub-circuit MOS transistor. As a result, the electrical noise coupling to the substrate is reduced, the RF/analog input signals are improved, and the leakage at the I/O pad is (greatly) reduced.
The integrated circuit of the invention provides protection against one polarity of ESD stress by the connection of the I/O pad to the drain of the discharge sub-circuit MOS transistor, and concurrently against the opposite polarity of ESD stress by the connection to the anode of the forward diode.
The integrated circuit of the invention has a size correlation between the forward diode junction capacitance (which has a positive voltage coefficient) and the drive sub-circuit MOS transistor junction capacitance (which has a negative voltage coefficient). The combined capacitances are substantially constant with respect to the I/O pad voltage.
The integrated protection circuit of the invention has two accumulation capacitors, one of which is coupled between the I/O pad and the drive circuit MOS transistor, and the other is coupled between the diode and the drive circuit MOS transistor. Differential booting is thus provided to maintain uniform substrate bias.
It is a technical advantage of the present method of preventing ESD damage that it may be implemented using standard semiconductor processing techniques. The present ESD protection circuitry, therefore, does not add any processing time or expense to the IC.